Industry & Company Events

"Future Trends in Imaging Beyond the Mobile Market"

Dr. Amol Kalburge

Presenting: Ronen Hasnes, PDK Section Head | TowerJazz

Qin Lei

Erez Sarig - Director of BD & Marketing PM/MS BU

TowerJazz Dr. Paul Hurwitz will be taking part of the panel

By Dr. Paul Hurwitz

Masanobu Kumazaki

By: Ronen Hasnes

Samir Chaudhry - Director, Design Enablement, TowerJazz
James Pond (CTO, Lumerical)
Gilles Lamant (Distinguished Engineer, Cadence)
Pei-Der Tseng (Design Engineering Architect, Cadence Design Systems)
Rich Goldman (Head of Marketing, Lumerical)

Presentor: Dr. Amol Kalburge

AJ ElJallad - Senior Sales Director, Tower Semiconductor

6:00pm - 6:30pm Detroit
Online - https://2020.auto-sens.com/agenda/session/334233

Presenter: Mike Scott - Director, Tower Semiconductor USA Aerospace & Defense

Samir Chaudhry - Director, Design Enablement
Ofer Tamir - Senior Director Design Enablement
John Stabenow - Siemens Industries Software

https://events.sw.siemens.com/en-US/realizelive/agenda?agendaPath=session/542767

Abstract: Established and emerging wireless and wireline applications such as 5G, WiFi and 400-800G optical networking are driving the demand for highly optimized RFIC solutions. Typical RF/mmWave design flows rely on the use of multiple EDA tools often sourced from multiple EDA vendors. This is inherently inefficient and often error prone leading to delays in getting a product to market. In addition, there exist multiple combinations of design tools and flows that prevent a foundry from providing a golden reference flow that can be used by a large portions of the design community. In this paper we present a silicon validated unified RFIC design flow using the Virtuoso RF. The design flow is based on a high-power SP4T switch design in Tower Semiconductor’s CS18QT9x1 foundry technology. RF SOI switch designs offer a useful test-case for the Virtuoso RF design flow as they require co-design and co-optimization of both the silicon and the package which is a key strength of this design flow. The design flow will be used to present a consistent modeling and simulation methodology. A seamless hand-off between PDK provided model, metal interconnect extraction within the p-cell, metal interconnect modeling outside the p-cell using EMX and Clarity, and the flip-chip package will be presented, while maintaining a single unified database that is used for tape-out. Silicon validation of key small and large-signal metrics will be presented highlighting the importance of the tight interaction between foundry Virtuoso PDK and package modeling using EMX and Clarity.

https://events.cadence.com/event/70560da2-887d-4795-a8bc-1dcad2d95ca6/websitePage:a4c8ddce-9c7a-43e1-a4f8-2333a8e328a2

Abstract: The demand for silicon photonics technology is growing with popular applications such as datacom (5G), artificial intelligence (AI), sensing, quantum computing and autonomous driving due to the improved bandwidth, sensing capabilities and reduced power consumption of photonic devices. For a typical photonic integrated circuits (PICs) design, designers use a combination of silicon validated components from a process design kit (PDK) and custom components that adhere to the foundry process design rules. However, as component layout designs and simulations are typically performed using different design tools and platforms, it is challenging to maintain the components’ compliance with the foundry process, while creating accurate compact models for efficient simulations. With a goal to reduce the design cycle time of custom photonic components for PICs designs, this work demonstrates a design workflow that facilitates photonic component layout, device simulation, compact model generation, and circuit simulation. This workflow leverages design tools from Cadence and Ansys-Lumerical, and a foundry silicon photonics PDK (PH18) from Tower Semiconductor. In this workflow, physical layout is the initial step of a custom photonic component design, where the curvilinear/polygon-based component shapes are drawn in Cadence Virtuoso Layout Suite by using the PH18 PDK. To assist device simulations on a custom design, the PDK provides a process file that contains all the information necessary for Lumerical DEVICE Suite to directly generate a 3D model from the design layout and to simulate it accurately for the foundry process. The device simulation results can then be used by the Lumerical CML Compiler to automatically build high-quality optical compact models in both the Lumerical INTERCONNECT and Verilog-A formats for different stages of the PIC design flow.

https://events.cadence.com/event/70560da2-887d-4795-a8bc-1dcad2d95ca6/websitePage:a4c8ddce-9c7a-43e1-a4f8-2333a8e328a2

Speaker: Lei Qin, Vice President of China Operations, Tower Semiconductor Ltd.

Speaker: Ofer Tamir - Director Design Enablement
Tower Semiconductor

https://synopsys.cventevents.com/event/48327162-4c7a-4e73-bf36-c08c1a607724/websitePage:1d80d249-e24e-4581-bcca-43e24deda8c1?RefId=AEM%20Page

Speaker: Lei Qin, VP of China Operations, Tower Semiconductor Ltd.

Speaker: Min Wang, Sales & FAE Manager, Tower Semiconductor Ltd.

The CMOS image sensor landscape keeps evolving to address new applications, in Industry 4.0, medical, automotive or consumer imaging. CMOS foundries must adapt to the various ideas and concepts Image Sensor suppliers in order to stay relevant. In this talk, we will discuss some of the solutions developed by Foundries to expand the use of imaging technology, with examples in the fields:
• Infrared Imaging
• Charge domain BSI Global shutter solutions
• Above IC technologies going beyond Imaging.

Benoit Dupont, Sensors and Display Marketing Director at Tower Semiconductor

 
For agenda and additional details - Click here >

Charging damage from plasma processing can be reduced through process architecture and plasma process optimization, but not all damage can be prevented. Antenna area ratio design rules are commonly used in the semiconductor industry to ensure that the remaining charging does not damage circuits. Capturing all possible contributions to device damage in a few simple antenna design rules is not possible. The presence of a Buried Oxide layer and Deep trenches in TS18PM SOI platform further complicates the creation of practical antenna design rules. Such rules were not found in the literature. This work describes the topologies specific for TS18PM SOI and how the different schemes of antenna rules were built and coded.

Ofer Tamir, Managing Director for Design Enablement and Support

 
For agenda and additional details - Click here >

Abstract:
The current adoption of communications standards such as 5G-FR1, WiFi6/6E, WiFi7, etc. have placed strict tolerances on technologies servicing the Sub-6GHz bands. This in turn has increased the performance demands placed on FEMs for wireless applications; among these, are Noise Figure (NF) targets for the LNA devices. Technology suppliers have diligently kept pace with the industry demands and so far, have managed to meet measured transistor NFmin values of ~ 0.2-0.25dB at 5GHz. However, measuring NF values below this level has been proven quite difficult to achieve. In this session, we will cover the limitations seen with test equipment capabilities, environmental factors and test setup schemes that seem to contribute to this lower bound on noise measurements. Consequently, these circumstances have curbed any further progress in thermal-noise improvements for devices focused on Sub-6GHz bands. Future improvements in noise testing methodologies and/or capabilities at these bands are imperative to aid in any device performance improvement endeavors.
Authors: Allan Calvo, Samir Chaudhry, Chris Masse (Tower Semiconductor)